The present invention relates to the field of frequency divider circuits, and in particular, to a frequency divider circuit using an asynchronous slip request signal to divide a clock signal according to a programmable divide ratio.
Certain circuits utilize clock signals of various frequencies to provide a specified functionality. Often, the various frequency clock signals are produced from an input clock signal generated by a phase-locked loop circuit or other clock generation circuit. The input clock signal is used to produce the clock signals having lower frequencies. The frequencies of the generated clock signals depend upon the applications in which the clock signals are used.
For example, in display applications, clock signals of different frequencies provide the horizontal and vertical synchronization signals, the pixel clock signal, as well as other signals for producing an image on a screen. These signals are often phase-aligned with one another to ensure the integrity of the image on the screen. As display applications improve, these signals are required to operate at higher and higher frequencies.
Synchronous counters are often used in a frequency divider circuit to divide the input clock signal to produce the other signals necessary for display applications. Synchronous counters provide a relatively simple architecture for dividing a clock signal to achieve other signals of lower frequencies. Certain synchronous counters allow for a programmable divide ratio so that a clock signal may be divided by a chosen factor.
A possible limitation of synchronous counters is the ability to divide signals above a certain frequency. Since the operational frequencies of display circuits as well as other circuits continue to increase, it will be appreciated that enabling a high frequency signal to be divided by a programmable divide ratio allows for increased performance of these circuits.
The present invention is directed to a frequency divider circuit that utilizes an asynchronous slip request signal to divide a high frequency clock signal by a programmable divide ratio xe2x80x9cRxe2x80x9d. The frequency divider circuit divides the frequency (F) of input clock signal by factor of 2 to produce a divided, or half-frequency signal. A synchronous counter of the frequency divider circuit functionally divides the half-frequency signal according to the programmable divide ratio over 2 (xe2x80x9cR/2xe2x80x9d). Accordingly, the frequency divider circuit produces a desired output clock signal of a predetermined frequency according to the programmable divide ratio (e.g. xe2x80x9cF/Rxe2x80x9d). To compensate for the odd divide ratios, an asynchronous slip request signal is produced by the frequency divider circuit. An instance of the asynchronous slip signal notifies the frequency divider circuit to skip a transition of the half-frequency signal. Accordingly, the half-frequency signal has an odd number of transitions for each pulse of the output clock signal. The ability to generate both the odd and even divide ratios after the input clock signal is divided by a factor of 2, results in an output clock signal of various frequencies that is produced from an input clock signal of a high frequency according to a programmable divide ratio.
In addition, certain portions of the frequency divide circuit may be cascaded such that the input clock signal may be further divided to lower its frequency to a usable level. The frequency of the input clock signal may be continually divided until it reaches a level usable by a synchronous counter. A separate asynchronous slip request signal is generated by the frequency divider circuit for each division of the input clock signal frequency. The asynchronous slip request signals maintain the ability to generate an output clock signal having a frequency corresponding to both even and odd divide ratios of the input clock signal frequency. Accordingly, an output clock signal is produced that has a frequency corresponding to a programmable divide ratio of a high frequency input clock signal.
In accordance with one aspect of the invention, a method for dividing the frequency of an input clock signal according to a programmable divide ratio includes dividing the frequency of the input clock signal by a first factor to produce a divided signal, when a slip signal is inactive. The output clock signal is produced by functionally dividing the frequency of the divided signal by a second factor. The second factor is determined by the programmable divide ratio divided by the first factor such that the frequency of the output clock signal is related to the frequency of the input clock signal and the programmable divide ratio. An asynchronous slip request signal is generated when the programmable divide ratio is a non-multiple of the first factor. The asynchronous slip request signal activates the slip signal such that a transition of the divided signal is skipped.
In accordance with yet another aspect of the invention, a pulse is generated in response to the asynchronous slip request signal that has a width of a period of the input clock signal. A transition of the divided signal is skipped in response to the pulse, such that for each asynchronous slip request signal, a single transition of the divided signal is skipped. A half-frequency signal is produced by toggling between a high logic level and low logic level for each period of the input clock signal. The half-frequency signal holds state in response to the asynchronous slip request signal.
In accordance with still another aspect of the invention, additional half-frequency signals may be produced. Additional toggle circuits toggle between a high logic level and low logic level for each period of each proceeding half-frequency signal. Each additional toggle circuit produces a half-frequency signal. The last toggle circuit produces a signal that corresponds to the divided signal. A counter circuit produces a count signal that increments to a factor. The factor corresponds to the most significant bits of the programmable divide ratio. After counting to the factor, the counter circuit is reset. A pulse occurs on the output clock signal after the count signal reaches the factor. Additionally, the asynchronous slip request signal is produced when the least significant bit of the programmable divide ratio is a high logic level and the count signal has reached a predetermined value.
In accordance with another aspect of the invention, an apparatus for dividing a first frequency of an input clock signal according to a programmable divide ratio includes a half-frequency circuit and a divide ratio circuit. The half-frequency circuit is arranged to produce a half-frequency signal in response to the input clock signal when the slip signal is inactive. The half-frequency signal corresponds to a divide signal that has a second frequency that is determined by the first frequency divided by a base multiple.
The half-frequency circuit includes a synchronizer circuit, a one-shot generator, and a toggle circuit. The synchronizer circuit is arranged to synchronize the asynchronous slip request signal with the input clock signal. The one-shot generator is arranged to produce a slip signal associated with the asynchronous slip request signal. The toggle circuit is arranged to produce the divide signal. The divide signal toggles for each period of the input clock signal in response to the input clock signal and the slip signal. The divide signal skips a toggle in response to a pulse of the slip signal.
The divide ratio circuit is arranged to produce an output clock signal and at least one asynchronous slip request signal. The asynchronous slip request signal assists in causing a skip of at least one transition of the divided signal when the programmable divide ratio is another multiple other than the base multiple. The output clock signal has an associated third frequency corresponding to a programmable divide ratio of the first frequency.
The divide ratio circuit includes a counter circuit, a first and second comparator circuit, and a first and second logic circuit. The counter circuit is arranged to produce a count signal dependent on the programmable divide ratio. The first comparator circuit is arranged to compare the count signal to the most significant bits of the programmable divide ratio. The second comparator is arranged to compare the count signal to a predetermined value. The first logic circuit is arranged to produce the output clock signal in response to the comparison of the first comparator circuit. The second logic circuit is arranged to produce the asynchronous slip request signal in response to the comparison of the second comparator circuit and the least significant bit of the programmable divide ratio.